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x24c01a 1 obsolete product description the x24c01a is a cmos 1024 bit serial e 2 prom, internally organized 128 x 8. the x24c01a features a serial interface and software protocol allowing operation on a simple two wire bus. three address inputs allow up to eight devices to share a common two wire bus. xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. inherent data re- tention is greater than 100 years. available in an eight pin dip and soic package. features 2.7v to 5.5v power supply low power cmos ?ctive current less than 1 ma ?tandby current less than 50 a internally organized 128 x 8 self timed write cycle ?ypical write cycle time of 5 ms 2 wire serial interface ?idirectional data transfer protocol four byte page write operation ?inimizes total write time per byte high reliability ?ndurance: 100,000 cycles ?ata retention: 100 years new hardwire ?write control function ?xicor, 1991 patents pending characteristics subject to change without notice 1k x24c01a 128 x 8 bit serial e 2 prom preliminary information functional diagram 3841 fhd f01 start stop logic control logic slave address register +comparator h.v. generation timing & control word address counter xdec ydec d out ack e 2 prom 32x32 data register start cycle (8) v cc r/w pin (4) v ss (5) sda (6) scl (3) a 2 (2) a 1 (1) a 0 d out load inc ck 8 (7) wc 3841-1
x24c01a 2 obsolete product pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the guide- lines for calculating typical values of bus pull-up resistors graph. address (a 0 , a 1 , a 2 ) the address inputs are used to set the least significant three bits of the seven bit slave address. these inputs can be static or actively driven. if used statically they must be tied to v ss or v cc as appropriate. if actively driven, they must be driven to v ss or to v cc . write control ( wc ) the write control input controls the ability to write to the device. when wc is low (tied to v ss ) the x24c01a will be enabled to perform write operations. when wc is high (tied to v cc ) the internal high voltage circuitry will be disabled and all writes will be disabled. device operation the x24c01a supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the trans- fer is a master and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive opera- tions. therefore, the x24c01a will be considered a slave in all applications. v cc wc scl sda a 0 a 1 a 2 v ss 1 2 3 4 8 7 6 5 x24c01a pin configuration 3841 fhd f02 pin names symbol description a 0 ? 2 address inputs sda serial data scl serial clock wc write control v ss ground v cc +5v 3841 pgm t01 clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are re- served for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the x24c01a continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. dip/soic
x24c01a 3 obsolete product figure 1. data validity figure 2. definition of start and stop stop condition all communications must be terminated by a stop condi- tion, which is a low to high transition of sda when scl is high. the stop condition is also used by the x24c01a to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the x24c01a will respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been se- lected, the x24c01a will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the x24c01a will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the x24c01a will continue to transmit data. if an acknowledge is not detected, the x24c01a will terminate further data trans- missions. the master must then issue a stop condition to return the x24c01a to the standby power mode and place the device into a known state. figure 3. acknowledge response from receiver scl sda data stable data change 3841 fhd f05 3841 fhd f06 3841 fhd f07 scl from master data output from transmitter 1 89 data output from receiver start acknowledge scl sda start bit stop bit
x24c01a 4 obsolete product device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are the device type identifier (see figure 4). for the x24c01a this is fixed as 1010[b]. following the start condition, the x24c01a monitors the sda bus comparing the slave address being transmit- ted with its slave address (device type and state of a 0 , a 1 and a 2 inputs). upon a correct compare the x24c01a outputs an acknowledge on the sda line. depending on the state of the r/ w bit, the x24c01a will execute a read or write operation. write operations byte write for a write operation, the x24c01a requires a second address field. this address field is the word address, comprised of eight bits, providing access to any one of the 128 words of memory. note: the most significant bit is a don? care. upon receipt of the word address the x24c01a responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the x24c01a begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the x24c01a inputs are disabled, and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. figure 4. slave address the next three significant bits address a particular device. a system could have up to eight x24c01a devices on the bus (see figure 10). the eight addresses are defined by the state of the a 0 , a 1 and a 2 inputs. the last bit of the slave address defines the operation to be performed. when set to one a read operation is selected, when set to zero a write operation is selected. figure 5. byte write figure 6. page write 1 0 10a2 a1 a0 r/w device type identifier device address 3841 fhd f08 3841 fhd f09 bus activity: master sda line bus activity: x24c01a s t a r t slave address s s t o p p a c k a c k a c k word address data 3841 fhd f10 bus activity: master sda line bus activity: x24c01a s t a r t slave address s s t o p p a c k a c k a c k a c k a c k word address n d ata n data n? data n+3 note: in this example n = xxxx 0000 (b); x = 1 or 0
x24c01a 5 obsolete product page write the x24c01a is capable of an four byte page write operation. it is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to three more words. after the receipt of each word, the x24c01a will respond with an acknowledge. after the receipt of each word, the two low order address bits are internally incremented by one. the high order five bits of the address remain constant. if the master should transmit more than four words prior to generating the stop condition, the address counter will ?oll over and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowledge and data transfer sequence. acknowledge polling the disabling of the inputs, during the internal write operation, can be used to take advantage of the typical 5 ms write cycle time. once the stop condition is issued to indicate the end of the host? write operation the x24c01a initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the x24c01a is still busy with the write operation no ack will be returned. if the x24c01a has completed the write operation an ack will be returned and the master can then proceed with the next read or write operation (see flow 1). read operations read operations are initiated in the same manner as write operations with the exception that the r/ w bit of the slave address is set to a one. there are three basic read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of the read operation is not a ?on? care.?to terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. flow 1. ack polling sequence 3841 fhd f11 write operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed issue stop no yes yes proceed issue stop no
x24c01a 6 obsolete product current address read internally the x24c01a contains an address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/ w set to one, the x24c01a issues an acknowledge and transmits the eight bit word during the next eight clock cycles. the read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. refer to figure 7 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/ w bit set to one, the master must first perform a ?ummy?write operation. the mas- ter issues the start condition, and the slave address followed by the word address it is to read. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/ w bit set to one. this will be followed by an acknowledge from the x24c01a and then by the eight bit word. the read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. refer to figure 8 for the address, acknowledge and data transfer sequence. figure 7. current address read bus activity: master sda line bus activity: x24c01a s t a r t slave address s s t o p p a c k d ata 3841 fhd f12 figure 8. random read 3841 fhd f13 bus activity: master sda line bus activity: x24c01a s t a r t slave address s a c k s t a r t s word address n a c k slave address data n a c k s t o p p
x24c01a 7 obsolete product sequential read sequential read can be initiated as either a current address read or random access read. the first word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. the x24c01a continues to output data for each acknowledge received. the read operation is terminated by the master, by not responding with an acknowledge and by issuing a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 127), the counter ?olls over?to address 0 and the x24c01a continues to output data for each acknowl- edge received. refer to figure 9 for the address, ac- knowledge and data transfer sequence. figure 9. sequential read figure 10. typical system configuration 3841 fhd f14 3841 fhd f15 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl v cc bus activity: master sda line bus activity: x24c01a slave address a c k a c k data n+x s t o p p d ata n a c k data n+1 a c k data n+2
x24c01a 8 obsolete product absolute maximum ratings* temperature under bias .................. ?5 c to +135 c storage temperature ....................... ?5 c to +150 c voltage on any pin with respect to v ss ............................... ?.0v to +7v d.c. output current ............................................ 5 ma lead temperature (soldering, 10 seconds) ............................. 300 c *comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c70 c industrial ?0 c +85 c military ?5 c +125 c 3841 pgm t02 supply voltage limits x24c01a 4.5v to 5.5v x24c01a-3.5 3.5v to 5.5v x24c01a-3 3v 5.5v x24c01a-2.7 2.7v to 5.5v 3841 pgm t03 d.c. operating characteristics (over recommended operating conditions unless otherwise specified) limits symbol parameter min. max. units test conditions l cc1 power supply current 1 ma scl = v cc x 0.1/v cc x 0.9 levels (read) @ 100 khz, sda = open, all other inputs = gnd or v cc ?0.3v i cc2 power supply current 2 ma scl = v cc x 0.1/v cc x 0.9 levels (write) @ 100 khz, sda = open, all other inputs = gnd or v cc ?0.3v i sb (1) standby current 50 a scl = sda = v cc ?0.3v, all other inputs = gnd or v cc , v cc = 5.5v i sb (1) standby current 30 a scl = sda = v cc ?0.3v, all other inputs = gnd or v cc, v cc = 3.3v + 10% i li input leakage current 10 av in = gnd to v cc i lo output leakage current 10 av out = gnd to v cc v ll (2) input low voltage ?.0 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3 ma 3841 pgm t04 capacitance t a = 25 c, f = 1.0mhz, v cc = 5v symbol test max. units conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a 0 , a 1 , a 2 , scl, wc )6 pf v in = 0v 3841 pgm t06 notes: (1) must perform a stop command prior to measurement. (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically sampled and not 100% tested.
x24c01a 9 obsolete product a.c. conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 3841 pgm t07 note: (4) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are periodically sampled and not 100% tested. 3841 fhd f03 equivalent a.c. load circuit 3841 fhd f17 5.0v 1533 ? 100pf output read & write cycle limits symbol parameter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 s t buf time the bus must be free before a new transmission can start 4.7 s t hd:sta start condition hold time 4.0 s t low clock low period 4.7 s t high clock high period 4.0 s t su:sta start condition setup time 4.7 s t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 s t dh data out hold time 300 ns 3841 pgm t08 a.c. characteristics limits (over recommended operating conditions unless otherwise specified) bus timing power-up timing symbol parameter max. units t pur (4) power-up to read operation 1 ms t puw (4) power-up to write operation 5 ms 3841 pgm t09 t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high
x24c01a 10 obsolete product write cycle limits symbol parameter min. typ. (5) max. units t wr (6) write cycle time 5 10 ms 3841 pgm t10 the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the x24c01a bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. write cycle timing sda 8th bit word n ack t wr stop condition start condition x24c01a address scl 3841 fhd f04 guidelines for calculating typical values of bus pull-up resistors symbol table must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance outputs inputs wa veform 3841 fhd f16 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k ? ) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k ? notes: (5) typical values are for t a = 25 c and nominal supply voltage (5v). (6) t wr is the minimum cycle time from the system perspective when polling techniques are not used. it is the maximum time the device requires to perform the internal write operation.
x24c01a 11 obsolete product note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62) packaging information
x24c01a 12 obsolete product 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.41) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parenthesis in millimeters) packaging information
x24c01a 13 obsolete product ordering information limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xicor, inc. reserves the right to discontinue prod uction and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,88 3, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expe cted to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. device v cc limits blank = 5v 10% 3.5 = 3.5v to 5.5v 3 = 3.3 10% temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c m = military = ?5 c to +125 c package p = 8-lead plastic dip s8 = 8-lead soic x24c01a p t -v

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